Annihilating Nanoscale Defects

Researchers may have found a way for the semiconductor industry to hit miniaturization targets on time and without defects

Written byArgonne National Laboratory
| 4 min read
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Target dates are critical when the semiconductor industry adds small, enhanced features to our favorite devices by integrating advanced materials onto the surfaces of computer chips. Missing a target means postponing a device's release, which could cost a company millions of dollars or, worse, the loss of competitiveness and an entire industry. But meeting target dates can be challenging because the final integrated devices, which include billions of transistors, must be flawless—less than one defect per 100 square centimeters.

Researchers at the University of Chicago and the U.S. Department of Energy's (DOE's) Argonne National Laboratory, led by Juan de Pablo and Paul Nealey, may have found a way for the semiconductor industry to hit miniaturization targets on time and without defects.

Related article: A Different Type of 2D Semiconductor

To make microchips, de Pablo and Nealey's technique includes creating patterns on semiconductor surfaces that allow block copolymer molecules to self-assemble into specific shapes, but thinner and at much higher densities than those of the original pattern. The researchers can then use a lithography technique to create nano-trenches where conducting wire materials can be deposited.

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